| 000 -LEADER |
|---|
| fixed length control field |
01639cam a2200301 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
vtls003155664 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
MY-SjTCS |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200226114051.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
110218s2008 maua 001 0 eng |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780073380339 (hbk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0073380334 (hbk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780077211646 (hbk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0077211642 (hbk.) |
| 039 #9 - LEVEL OF BIBLIOGRAPHIC CONTROL AND CODING DETAIL [OBSOLETE] |
|---|
| Level of rules in bibliographic description |
201102181238 |
| Level of effort used to assign nonsubject heading access points |
VLOAD |
| Level of effort used to assign subject headings |
201102181235 |
| Level of effort used to assign classification |
VLOAD |
| Level of effort used to assign subject headings |
201007281348 |
| Level of effort used to assign classification |
pushpa |
| Level of effort used to assign subject headings |
201007131220 |
| Level of effort used to assign classification |
wilmina |
| -- |
201004051035 |
| -- |
meena |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Item number |
BRO 2008 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Brown, Stephen D. |
| 9 (RLIN) |
20696 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Fundamentals of digital logic with Verilog design / |
| Statement of responsibility, etc. |
Stephen Brown and Zvonko Vranesic. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Boston : |
| Name of publisher, distributor, etc. |
McGraw-Hill Higher Education, |
| Date of publication, distribution, etc. |
c2008. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xix, 935 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. + |
| Accompanying material |
1 CD-ROM (4 3/4 in.) |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Design concepts - 2. Introduction to logic circuits - 3. Implementation technology - 4. Optimized implementation of logic functions - 5. Number representation and arithmetic cirucits - 6. Combinational-circuit building blocks - 7. Flip-flops, registers, counters, and a simple processor - 8. Synchronous sequential circuits - 9. Asynchronous sequential circuits - 10. Digital system design - 11. Testing of logic circuits - 12. Computer aided design tools. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic circuits |
| General subdivision |
Design and construction |
| -- |
Data processing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 9 (RLIN) |
18798 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer-aided design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Vranesic, Zvonko G. |
| 9 (RLIN) |
8456 |
| 920 ## - Programme |
|---|
| Programme |
ENG : 147080, 147493, 147494, 147079, 147495, 147082, 147081, 147497 |
| 999 ## - SYSTEM CONTROL NUMBERS (KOHA) |
|---|
| Koha biblionumber |
126568 |
| Koha biblioitemnumber |
126568 |
