Verification by error modeling [electronic resource] : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.
By: Radecka, Katarzyna.
Contributor(s): Zilic, Zeljko | ebrary, Inc
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Series: Frontiers in electronic testing: 25.Publisher: Boston : Kluwer Academic Publishers, 2003Description: xiv, 216 p. : ill. ; 25 cm.Subject(s): Integrated circuits -- Very large scale integration -- Computer-aided design | Integrated circuits -- Verification | Error analysis (Mathematics)Genre/Form: Electronic books.DDC classification: 621.39/5 Online resources: An electronic book accessible through the World Wide Web; click to view
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
| 621.39/5 (Browse shelf) | Available |
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Includes bibliographical references and index.
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Electronic reproduction. Palo Alto, Calif. : ebrary, 2009. Available via World Wide Web. Access may be limited to ebrary affiliated libraries.