System-on-chip test architectures  nanometer design for testability /  [electronic resource] : 
edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. 
 - Amsterdam ;  Boston :  Morgan Kaufmann Publishers,  c2008. 
 - xxxvi, 856 p. :  ill. ;  25 cm. 
 - The Morgan Kaufmann series in systems on silicon .
 - Morgan Kaufmann series in systems on silicon. .
<br/><br/>Includes bibliographical references and index. 
<br/><br/><br/>Electronic reproduction. <br/>Palo Alto, Calif. : <br/>ebrary, <br/>2009. <br/>Available via World Wide Web. <br/>Access may be limited to ebrary affiliated libraries. 
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<br/><br/><label>Subjects--Topical Terms: </label><br/>Systems on a chip--Testing.<br/>Integrated circuits--Very large scale integration--Testing.<br/>Integrated circuits--Very large scale integration--Design.
<br/><br/><label>Index Terms--Genre/Form: </label><br/>Electronic books.
<br/><br/><label>LC Class. No.: </label>TK7895.E42  / S978 2008eb 
<br/><br/><label>Dewey Class. No.: </label>621.39/5