000			01616nam a22003734a 4500
001			vtls003176054
003			MY-SjTCS
005			20200226112000.0
006			m u
007			cr cn|||||||||
008			100712s2003 maua sb 001 0 eng
020			_z1402076525 (alk. paper)
035			_a(CaPaEBR)ebr10088540
039		9	_y201007121444 _zVLOAD
040			_aCaPaEBR _cCaPaEBR
050	1	4	_aTK7874.75 _b.R33 2003eb
082	0	4	_a621.39/5 _222
100	1		_aRadecka, Katarzyna.
245	1	0	_aVerification by error modeling _h[electronic resource] : _busing testing techniques in hardware verification / _cwritten by Katarzyna Radecka, Zeljko Zilic.
260			_aBoston : _bKluwer Academic Publishers, _c2003.
300			_axiv, 216 p. : _bill. ; _c25 cm.
490	1		_aFrontiers in electronic testing ; _v25
504			_aIncludes bibliographical references and index.
529			_aTSLHHL
533			_aElectronic reproduction. _bPalo Alto, Calif. : _cebrary, _d2009. _nAvailable via World Wide Web. _nAccess may be limited to ebrary affiliated libraries.
650		0	_aIntegrated circuits _xVery large scale integration _xComputer-aided design.
650		0	_aIntegrated circuits _xVerification. _940219
650		0	_aError analysis (Mathematics)
655		7	_aElectronic books. _2local
700	1		_aZilic, Zeljko.
710	2		_aebrary, Inc. _925628
830		0	_aFrontiers in electronic testing ; _v25.
856	4	0	_uhttp://ezproxy.taylors.edu.my/login?url=http://site.ebrary.com/lib/taylorscollege/Doc?id=10088540 _zAn electronic book accessible through the World Wide Web; click to view
999			_c88362 _d88362